1. Field of the Invention
The invention relates to image sensors. More particularly, the invention relates to correcting readout from a defective column or row.
2. The State of the Art
One problem camera systems have with image capture is correcting defective columns on the image sensor. The problem is worsened by a charge-sharing readout bus architecture because a defective column can affect the readout for adjacent, non-defective columns. If the defect is limited to the linear range of operation of the imager, then the defect can be corrected with image processing, but defective columns typically drive the signal out of the linear region. When a column filter is applied, there is still an artifact in the final image, around the bad column, due to the errors introduced by the non-linearity. Consequently, the image processing software has difficulty correcting for defective columns. One solution is to select chips with no defective columns, however this reduces chip yield and increases cost of the imagers.
Defective columns may be caused by localized nano-Amp (nA) level junction leakage which do not cause yield problems for other CMOS products, therefore there is less incentive to CMOS manufacturers to reduce this type of failure.
FIG. 1a is a schematic diagram illustrating one prior art example for reading data from columns of an imager chip onto a video bus. FIG. 1 represents part of the column outputs for a typical sensor. Columns 10-1, 10-2, and 10-3 connect to data inputs, for example photodetectors and amplifiers (not shown). Load line 15 is connected to the gate of storage transistors 20-1, 20-2, and 20-3. When load line 15 is high, storage transistors 20 are biased into an active state, or turned on, and voltage from columns 10-1, 10-2 and 10-3 charges storage capacitors 25-1, 25-2, and 25-3, respectively. When load line 15 goes low, storage transistors 20 are turned off and storage capacitors 25 hold a charge set by the column voltage sampled during the time load line 15 was high.
Select transistors 30-1, 30-2, and 30-3 are connected to storage capacitors 25 and AND gates 35-1, 35-2, and 35-3. AND gates 35 are each connected to decoder 40 and thereby to address generator 45. Address generator 45 generates an address for a particular column, which is sent to decoder 40. Decoder 40 then decodes the address and sends an output line high. For example, if address generator 45 generated the address for column 10-1, then decoder would drive line 50-1 to AND gate 35-1 to go high. If address generator 45 generated the address for column 10-2 then decoder would drive line 50-2 to AND gate 35-2 to go high, and line 50-3 to AND gate 35-3 for column 10-3.
If column enable 55 is also high, then whichever AND gate 35 has both inputs high will drive its output high and turn on select transistor 30. The charge on storage capacitor 25 redistributes through video bus 60 to video bus capacitor 65. After this redistribution, column enable 55 goes low, driving AND gate 35 low and turning off select transistor 30. Charge stabilizes on video bus capacitor 65 and can then be read out through buffer amplifier 70 to an output. The process is repeated for each column.
With respect to defective rows, a sequential readout pixel has less column outputs, but more row access wires. The row wires are low impedance nodes that are not susceptible to low level leakage, only hard shorts or opens that would cause failures with any CMOS product. A hard short on the row wires will cause global problems that may have an effect on image quality or other imager characteristics such as power consumption or gradients. For example, two rows shorted together should not be driven at opposite logic levels.
FIG. 1b is a schematic diagram illustrating one prior art example for reading data from rows of an imager chip. Rows 75 connect to transistors 80, which connect to each of their respective columns (not shown). Row 75-1 is one example of a row with no defect. An assertion or deassertion on row 75-1 will affect each transistor coupled to row 75-1. Rows 75-2 and 75-3 illustrate one example of a shorting defect, where short 85 connects rows 75-2 and 75-3 together. Asserting one of the rows will also assert the other due to short 85, resulting in an incorrect readout for the pixels along both rows.
FIG. 2 is a prior art graph for the signal and voltage levels while reading data from columns, related to FIG. 1a. Pulse 200 represents high voltage on load line 15. Consequently, capacitors 25 store charge from columns 10. Charge storing, or voltage sampling, stops when pulse 200 goes low. Pulse 205 signals a readout from storage capacitor 25-1 on column 10-1 to video bus capacitor 65. Pulse 205 represents high voltage on column enable 55.
Video bus waveform 210 represents voltage across video bus capacitor 65. Column enable 55 goes low (low voltage), as represented by pulse 205 going low, and charge stops accumulating on video bus capacitor 65. Voltage on column 10-1 is determined by comparing the voltage on video bus 60 prior to pulse 205, for example point 218, with voltage on video bus 60 after pulse 205, for example point 215. This is one example of charge sharing.
Charge sharing operates as follows. For each row, all column lines are discharged to ground using the load device as a column reset switch. The column reset switch is then turned off and the row select line is activated for a predetermined length of time, connecting the amplifiers in the pixel sensors to the column lines, where they charge the column lines' capacitance. The voltages on the column lines approach the final value approximately logarithmically after the source follower transistor enters its sub-threshold regime, about 60 mV per common log unit of the length of time they are turned on.
After a predetermined time, the pixels are disconnected from the columns. The column lines are charged to voltages in a known predetermined relation to the signals at the inputs of the pixel sensor amplifiers, with random variations that depend on the particular amplifiers but not on the column lines. One column line at a time is then selected to be connected to the video bus, sharing the charges between the selected column line and the video bus, and thereby creating a very linear discrete-time filtered version of the sequence of column signals across the row, with little or no dependence on the rate or duration of the column select signals. The design and timing of the column decoder that drives the column select switches must be done with care, as known in the art, to assure that no glitches occur, because glitches may cause unwanted sharing of charge with columns that should not be selected.
Continuing with the example, pulse 220 signals readout for column 10-2, resulting in transition 225, in which the video bus voltage ends at point 230. Voltage on column 10-2 is determined by comparing voltage on video bus 60 at point 215 to voltage at point 230. Pulse 235 signals readout for column 10-3, resulting in transition 240 to point 245. Voltage on column 10-3 is determined by comparing voltage on video bus 60 at point 230 to voltage at point 245.
FIG. 3 is a prior art graph for the signal and charge levels while reading data with a defective column, related to FIG. 1. In this example, column 10-1 is defective. Pulse 300 connects capacitor 25-1 with video bus capacitor 65. Video bus waveform 305 represents voltage across video bus capacitor 65 and point 310 represents the voltage after pulse 300 goes low. Point 310 is above boundary 315. Boundaries 315 and 320 represent the high and low limits of normal range, where photocharge to output voltage is approximately linear. Column filters (not shown) do not correct for errors introduced when voltage moves beyond the linear range. Column filtering is typically a mathematical operation that corrects charge readout in a charge-sharing architecture as opposed to reset readout.
Pulse 325 causes the readout for column 10-2, resulting in transition 330 in which the video bus voltage ends at point 335. Voltage on column 10-2 is determined by comparing voltage on video bus 60 at point 310 to point 335. Voltage is still above boundary 315, resulting in more corrupted data. Pulse 340 signals readout for column 10-3, resulting in transition 345 to point 350. Voltage on column 10-3 is determined by comparing voltage on video bus 60 at point 335 to point 350. Because point 335 is outside the linear range, an accurate value for voltage across column 10-3 cannot be determined. Many of the pixels on a row following a bad column will have corrupted data values due to the above reasons.
Another problem arises when rows are shorted together. When two rows are shorted together, either one gets pulled high which also pulls the other high, or one is pulled high while another is being pulled low, creating a conflict.